The present invention relates to an integrated circuit device, and more particularly to a semiconductor device, in which a bipolar transistor having a high operation speed and a MOS transistor having a small size are formed on the same substrate so as to make an integrated circuit.
A conventional semiconductor device, in which a bipolar transistor and a MOS transistor are formed on the same substrate, is discussed on pages 1115 to 1123 of the IEICE (Institute of Electronics, Information and Communication Engineers of Japan) Technical Report C, Vol. J70-C, No. 8, August, 1987. A semiconductor device in which a bipolar transistor and a MOS transistor is disclosed also in U.S. patent application, Ser. No. 554,794, filed Nov. 23, 1983 now U.S. Pat. No. 5,208,589. FIG. 2A is a sectional view showing the above semiconductor device, and FIG. 2B shows the impurity concentration distribution at the cross section taken along the line A--A' of FIG. 2A. Referring to FIG. 2A, each of first semiconductor regions 2 and 5 includes a P.sup.+ -buried layer 20 and a P-diffusion layer 21. The P-diffusion layer 21 is produced by the diffusion of a P-type impurity from the surface of the layer 21. An N-channel MOS transistor 60 is formed in the first semiconductor region 2. Each of second semiconductor regions 3 and 4 includes an N.sup.+ -buried layer (that is, heavily-doped N-buried layer) 30 and an N-diffusion layer 31. An NPN bipolar transistor 70 and a P-channel MOS transistor 80 are formed in the second semiconductor regions 3 and 4, respectively. The P+-buried layer 20 and P-diffusion layer 21 of the first semiconductor region 5 are interposed between the second semiconductor regions 3 and 4 to electrically isolate these regions 3 and 4 from each other. The impurity concentration in the first semiconductor region 2 becomes minimum at a depth, as shown in FIG. 2B.
When a bipolar transistor having a high operation speed and a MOS transistor having a small size are formed on the same substrate in the above-mentioned manner, it is impossible to make the size of the MOS transistor smaller than a limit. The reason for this will be explained below. In the first semiconductor region 2 of FIG. 2A, as shown in FIG. 2B, a lightly-doped layer is formed at the connecting portion between the P-diffusion layer 21 which is formed by the diffusion of a P-type impurity from the surface of the first semiconductor region, and the P.sup.+ -buried layer 20. Accordingly, the depletion layer generated at each of the source and drain of the MOS transistor which is formed in the first semiconductor region, is enlarged at the above-mentioned, lightly-doped layer. Thus, the punch-through is generated, and a threshold voltage is lowered. That is, the short channel characteristics of the MOS transistor are deteriorated. Accordingly, it is difficult to form an integrated circuit by using a MOS transistor with a small gate length. This problem can be solved by increasing the impurity concentration of the P.sup.+ -buried layer 20 as indicated by a dashed curve in FIG. 2B, thereby enhancing the impurity concentration of lightly-doped layer. The method, however, has the following drawback, and cannot be used. As can be seen from FIG. 2A, a main function of the P.sup.+ -buried layer 20 is to electrically isolate two N.sup.+ -buried layers 30 from each other. In this point, an increase in the impurity concentration of the P.sup.+ -buried layer 20 will cause no trouble. While, the N.sup.+ -buried layer 30 acts as the collector layer of the bipolar transistor. In order to operate a circuit which includes the bipolar transistor, at high speed, it is necessary to make substrate capacitance C.sub.TS which is produced between the above collector layer and a P-substrate, as small as possible. The substrate capacitance C.sub.TS is usually divided into two components, that is, a bottom component which is produced between the bottom of the N.sup.+-buried layer 30 and the P-substrate 1, and a side component which is produced between the side face of the N.sup.+ -buried layer 30 and the P.sup.+ -buried layer 20. Owing to the difference in impurity concentration between the P.sup.+ -buried layer 20 and the P-substrate 1, the side component of the substrate capacitance C.sub.TS is far greater than the bottom component thereof. Accordingly, when the impurity concentration of the P.sup.+ -buried layer 20 is increased, the side component is increased, and the substrate capacitance C.sub.TS is also increased. Thus, the operation speed of the circuit including the bipolar transistor is greatly reduced.
Accordingly, in a case where an integrated circuit including a MOS transistor with a small channel length and a high-speed bipolar transistor with small substrate capacitance C.sub.TS is formed as shown in FIG. 2A, it is impossible to make the channel length of the MOS transistor less than a limit, and thus a MOS transistor having satisfactory performance cannot be formed.